USA - Austin, Texas: Senior Layout Designer

Job Title: Senior Layout Designer Location: Austin, Texas, USA Position Type: Full-Time Contract (Direct Placement / Project Deployment) Openings: 1 Position Available Experience Required: 10 to 15 Years Payment Terms: 105 Days Net Replacement Terms: 90 Days --- About the Project & Opportunity Our UK based international recruitment agency is managing a specialized hardware engineering deployment project for a leading semiconductor and technology enterprise in Austin, Texas, one of the premier silicon engineering hubs in the United States. We are actively seeking one (1) highly accomplished Senior Layout Designer to join the engineering team. This project is tailored for a veteran layout specialist possessing a deep background in advanced silicon nodes. You will take technical ownership over complex integrated circuit (IC) physical designs, ensuring maximum performance, optimal area efficiency, and flawless tape-out execution. What You Will Do - Lead the custom physical layout design of high-performance analog, digital, mixed-signal, or RF integrated circuits (ICs) from floorplanning through to final verification. - Execute complex floorplanning, power-grid routing, and critical signal routing under aggressive performance, noise, and space constraints. - Perform rigorous physical verification checks including Design Rule Checking (DRC), Layout Versus Schematic (LVS), Antenna, and Electromigration (EM) analyses using industry-standard EDA tools. - Collaborate closely with circuit design engineers to interpret schematics, mitigate parasitic effects, and resolve intricate layout and architectural roadblocks. - Drive layout optimization across advanced sub-micron process nodes, ensuring strict adherence to foundry design rules and manufacturing tolerances. What We Are Looking For (Compliance & Requirements) - Technical Experience: 10 to 15 years of progressive, hands-on experience specializing in custom IC layout design within a semiconductor environment. - Node Familiarity: Deep expertise working with advanced deep sub-micron technologies and multi-layer process nodes. - Tool Mastery: Expert-level proficiency with major EDA software suites (such as Cadence Virtuoso, Calibre, or Synopsys tools). - Validation Skills: A rock-solid understanding of deep sub-micron layout challenges, matching techniques, parasitic reduction, and physical verification infrastructure. - Core Attributes: Exceptional attention to detail, a proven track record of successful silicon tape-outs, and the capability to work efficiently under strict project development deadlines. Next Steps for Applicants As the managing recruitment partner, our international mobilization team will guide qualified candidates through technical layout portfolio reviews, engineering screening panels, and US visa deployment/onboarding compliance pathways.